The present invention relates to technology on bipolar-MOS (BiMOS) devices, and more particularly to an integrated circuit semiconductor device and an electronic apparatus using the device, the device including an internal voltage generating means for generating an internal voltage from an external power source voltage of a potential higher than the internal voltage and providing a power source for internal circuits.
Integrated circuit semiconductor devices, typically CMOS transistors, are generally powered with a 5 V power source.
The electric field in circuit elements becomes higher as the elements become finer. Change in the threshold voltage of MOS transistors, occurrence of punch-through, and the like are dependent upon the electric field. The electric field therefore has significant influences upon the element performance and reliability. For this reason, it is difficult for 0.5 micron or finer circuit elements to be operated with a 5 V power source. It is anticipated that a power source having a voltage of about 3.3 V will be used for such finer circuit elements.
Generally electronic circuits are presently driven with a standard 5 V power source. It becomes therefore necessary for semiconductor integrated circuits to internally generate a lower voltage power source by using the standard 5 V power source.
FIG. 12 is a circuit diagram showing an example of a conventional semiconductor integrated circuit having an internal voltage generating circuit. In FIG. 12, a reference numeral 1200 represents a semiconductor chip, and 1201 an NPN transistor (hereinafter simply called NPN). Reference numeral 1202 represents a parasitic collector resistance of NPN 1201, 1203 an external power source input terminal, 1204 a voltage detecting means formed of resistors R1 and R2, 1205 an amplifier, 1206 a reference voltage generator, 1207 an internal circuit formed of a P-channel MOS transistor (hereinafter simply called PMOS) M1 and an N-channel MOS transistor (hereinafter simply called NMOS) M2, Cw a capacitance at the emitter output line of NPN 1201.
In this semiconductor integrated circuit, an output from the reference voltage generator 1206 is compared with an output from the voltage detecting means 1204, and the output from the amplifier 1205 is used for the control of the base drive current of NPN 1201 to thereby obtain a predetermined output voltage.
FIG. 13 is a cross section of NPN, PMOS and NMOS of the circuit shown in FIG. 12. In FIG. 13, a reference numeral 1300 represents an N-type semiconductor substrate, and 1301 and 1302 P-type wells. The N-type substrate forms the collector of NPN 1201, the P-type well 1301 the base, an N.sup.+ diffused layer 1303 the emitter, and N.sup.+ and P.sup.+ diffused layers 1304 and 1305 the collector and base electrodes, respectively. Reference numerals 1306 and 1307 represent the collector parasitic resistances rc.sub.1 and rc.sub.2 of NPN 1201 which correspond to resistance rc 1202 shown in FIG. 12. P.sup.+ diffused layers 1308 and 1309 form the source and drain electrodes of PMOS, and a polysilicon 1310 forms the gate electrode. A P-type well 1302 forms the substrate of NMOS, N.sup.+ diffused layers 1311 and 1312 form the drain and source electrodes, respectively and polysilicon 1313 forms the gate electrode.
FIG. 14 is a circuit diagram showing another example of a conventional semiconductor integrated circuit having an internal voltage generating circuit. In FIG. 14, a reference numeral 1400 represents a semiconductor chip, and 1401 a PNP transistor (hereinafter simply called PNP). Reference numeral 1402 represents a parasitic collector resistance of PNP 1401, 1403 an external power source input terminal, 1404 a voltage detecting means composed of resistors R1 and R2, 1405 an amplifier, 1406 a reference voltage generator, 1407 an internal circuit composed of PMOS M1 and NMOS M2, Cw a capacitance at the emitter line of PNP 1401.
In this semiconductor integrated circuit, an output from the reference voltage generator 1406 is compared with an output from the voltage detecting means 1404, and the output from the amplifier 1405 is used for the control of the base current drive of PNP 1401 to thereby obtain a predetermined output voltage.
FIG. 15 is a cross section of PNP, PMOS and NMOS of the circuit shown in FIG. 14. In FIG. 15, reference numeral 1500 represents a P-type semiconductor substrate, and 1501 and 1502 N-type wells. The P-type substrate forms the collector of PNP 1401, the N-type well 1501 the base, a P.sup.+ diffused layer 1503 the emitter, and P.sup.+ and N.sup.+ diffused layers 1504 and 1503 the collector and base electrodes, respectively. Reference numerals 1506 and 1507 represent the collector parasitic resistances rc.sub.1 and rc.sub.2 of PNP 1401 which correspond to resistance rc 1402 shown in FIG. 14.
N.sup.+ diffused layers 1508 and 1509 form the source and drain electrodes of NMOS, and a polysilicon 1510 the gate electrode. An N-type well 1502 forms the substrate of PMOS, P.sup.+ diffused layers 1511 and 1512 the drain and source electrodes, and polysilicon 1513 the gate electrode.
The above conventional circuits are disclosed in, for example, Japanese Patent Laid-open Publication JP-A-59-178763 laid open on Oct. 11, 1984.
The internal voltage generating circuit fabricated within a semiconductor integrated circuit must satisfy at least the following requirements:
(1) A power source current should not pass through the semiconductor substrate.
The reason for this is that if a power source current flows into the semiconductor substrate, the substrate potential will fluctuate to cause a latch-up or an undesired coupling to internal circuits.
(2) A difference between the internal voltage of the internal voltage generating circuit and the external power source voltage should not be too large a value when the internal voltage generating circuit supplies a predetermined load current.
The reason for this requirement is that if the internal voltage is set at 3.3 V, for example, by using a standard 5 V external power source, a voltage drop of 1.7 V only is permitted, otherwise a non-standard power source having a voltage higher than 5 V is required.
(3) Noise superposed on the internal voltage of the internal voltage generating circuit as a result of the switching operation of load internal circuits can be eliminated satisfactorily.
The reason for this requirement is that noise which is superposed on the power source will increase because of an icnrease in the switching rate as the circuit elements are made finer and highly sophisticated. Further, since the noise margin of the internal circuit becomes small if a lower power source voltage is used, it is impossible to eliminate power source noise satisfactorily.
As understood from the above requirements, the circuit structure shown in FIG. 13 is associated with the problem that a power source current passage from the external power source Vin to the internal power source Vout is formed within the N-type semiconductor substrate 1300.
Further, the semiconductor substrate 1300 generally of a low impurity concentration has large collector parasitic resistances rc.sub.1 and rc.sub.2. The collector parasitic resistances rc.sub.1 and rc.sub.2 are desired to have a predetermined value because of the following reason. Specifically, the condition is expressed by: EQU Vin.gtoreq.Vout+V.sub.BE +I.sub.L .times.rc
for maintaining an active state (unsaturated operation region) of NPN transistor 1601 shown in the voltage drop circuit portion of FIG. 16, where Vin represents the input voltage from the external power source, and Vout the output voltage from the internal power source. FIG. 17 shows the relationship between a load current IL and a lower limit of the external power source voltage Vin, using the collector parasitic resistance rc as parameters. As seen from FIG. 17, if, for example, the external power source voltage Vin is 5 V and the internal power source voltage Vout is 3.3 V, then the collector parasitic resistance should be made smaller than 10 ohms in order to allow the load current I.sub.L of 100 mA.
Such requirements are also applicable to the circuit structure shown in FIG. 14.
JP-A-57-107560 laid open on Jun. 21, 1984 discloses an LSI made of fine MOS transistors and having a low voltage regulator therein. The above-described problem, howver is not considered in its disclosure.